Hybrid Memory Cube concept DRAM 128GB per second

The closing keynote, given by CTO Justin Rattner, has provided an opportunity to see some of the projects in which Intel is committed to the future of computing. Among several changes, including some related to programming, we remind the concept Hybrid Memory Cube, which raises the energy efficiency of more than 7 times compared to current technologies.



The bandwidth achieved by the prototype, fully functional and shown on the stage, reaching the impressive value of 128GB per second of bandwidth, 12 times greater than that afforded by the DDR3-1333 4GB ECC taken as reference. It can be seen also as the VDD Voltage Drain, is contained at 1.2 V, at 1.5 and 3.3 modules just mentioned V of PC133 SDRAM. Also note the very low value of energy per bit, just 8pj content.



Hybrid Memory Cube uses configuration memory chips overlapped layers that form a cube. To connect the chips together we find a new memory interface that raises high-efficiency standards of energy consumption per bit. The concept shown DRAM was developed by Intel in collaboration with Micron, and it seems that the new approach to design brings several benefits.



The practical test carried out on the stage showed a value equal to 121GB of bandwidth per second, compared with 128 reported. We can not speak of "fail", since we are talking about very high levels of bandwidth, obtained from the other with very low voltages and a technology already in operation. These advances should not take long to make its entry into commercial products, although they have been given guidance on.

Posted by: Wasim Javed